The present invention is directed to integrated circuits. More particularly, the invention provides a method and system for device characterization with array and decoder. Merely by way of example, the invention has been applied to testing MOS transistors. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as a given process, device layout, and/or system design often work down to only a certain feature size.
An example of such a limit is characterization of MOS transistors. The MOS transistors have various gate lengths and gate widths. Conventionally, each transistor is connected to at least one separate pad. For example, each transistor includes four terminals for the gate, the source, the drain, and the substrate respectively, and these four terminals are connected to four pads respectively. Different transistors do not share the same pads. Hence the pad area is much larger than the device area. The total area for the pad area and the device area can be too large.
From the above, it is seen that an improved technique for characterizing MOS transistors is desired.